Qwenputer: claimed RISC-V CPU inside the Qwen3.5-4B weights
A post by @divagr1925 describes a Qwen3.5-4B that, according to the author, runs C and MicroPython using Gated DeltaNet layers as memory. The author's benchmark claims have not been verified.
By Wendelmaques Pereira · Updated today
Source: Qwenputer: CPU RISC-V embutida nos pesos do Qwen3.5-4B (x.com). Text prepared with AI from this source.
What happened and what to do
The post by @divagr1925 presents the Qwenputer. According to the author, a Qwen3.5-4B model has a RISC-V CPU encoded in its own weights. As described, the Gated DeltaNet layers act as RAM, allowing C and MicroPython code to run during forward passes. The author also shows the use of Gated DeltaNet state as general-purpose memory. The author's benchmark claims have not been verified.
For a company, the practical point is not to adopt the technique but to treat the claim as a hypothesis to test. A reproducible evaluation pipeline could run the cited checkpoint on private infrastructure, record inputs, outputs, execution time and resource use, and compare the results against baselines, with versioning of weights and prompts. In parallel, provenance monitoring is worthwhile: verify model file hashes, origin and licenses before any production use. That way the decision rests on measurements, not isolated demonstrations.
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